Test MP+dmb.sy+addr-[fr-rf]-ctrl-fri-rfi

AArch64 MP+dmb.sy+addr-[fr-rf]-ctrl-fri-rfi
"DMB.SYdWW Rfe DpAddrdR FrLeave RfBack DpCtrldR Fri Rfi Fre"
Cycle=Rfi Fre DMB.SYdWW Rfe DpAddrdR FrLeave RfBack DpCtrldR Fri
Relax=
Safe=Rfi Rfe Fri Fre DMB.SYdWW DpAddrdR DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR FrLeave RfBack DpCtrldR Fri Rfi Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X7=x;
2:X1=z;
}
 P0          | P1                  | P2          ;
 MOV W0,#2   | LDR W0,[X1]         | MOV W0,#1   ;
 STR W0,[X1] | EOR W2,W0,W0        | STR W0,[X1] ;
 DMB SY      | LDR W3,[X4,W2,SXTW] |             ;
 MOV W2,#1   | LDR W5,[X4]         |             ;
 STR W2,[X3] | CBNZ W5,LC00        |             ;
             | LC00:               |             ;
             | LDR W6,[X7]         |             ;
             | MOV W8,#1           |             ;
             | STR W8,[X7]         |             ;
             | LDR W9,[X7]         |             ;
Observed
    z=1; y=1; x=1; 1:X9=1; 1:X6=2; 1:X5=0; 1:X3=1; 1:X0=1;
and z=1; y=1; x=1; 1:X9=1; 1:X6=0; 1:X5=0; 1:X3=1; 1:X0=1;
and z=1; y=1; x=1; 1:X9=1; 1:X6=2; 1:X5=0; 1:X3=1; 1:X0=0;
and z=1; y=1; x=2; 1:X9=2; 1:X6=0; 1:X5=0; 1:X3=1; 1:X0=0;
and z=1; y=1; x=2; 1:X9=1; 1:X6=0; 1:X5=0; 1:X3=1; 1:X0=0;
and z=1; y=1; x=1; 1:X9=1; 1:X6=0; 1:X5=0; 1:X3=1; 1:X0=0;